TY  - BOOK
AU  - Cavanagh , Joseph
TI  - Verilog HDL Design Examples
SN  - 9781351596305
PY  - 2018///
CY  - London
PB  - T&F
KW  - CSE
KW  - Verilog HDL Design Examples
UR  - https://www.taylorfrancis.com/books/9781351596305
ER  -